Senior Verification Engineer
Source: Himalayas
Tailor your resume to this posting—match keywords and layout for recruiters. Try Resume.io before you apply.
AI Summary Powered by Gemini
This Senior Verification Engineer role involves leading the verification of complex SoC designs using UVM and SystemVerilog. It is an ideal opportunity for experienced engineers to influence architectural quality and pre-silicon validation in a fully remote environment.
Job Description
We’re looking for a Senior Verification Engineer to play a key role in verifying complex SoC and subsystem designs. You’ll work hands-on with design and architecture teams to ensure functionality, quality, and coverage goals are met across multiple projects.ResponsibilitiesAnalyze architectural specifications and define verification requirements.Develop and maintain UVM-based verification environments.Create detailed test plans and develop corresponding test cases.Debug functional issues and contribute to root-cause analysis.Collaborate closely with design and architecture teams to align milestones and quality metrics.QualificationsBachelor’s or Master’s degree in EE, CS, or a related field.7–10+ years of experience in verification or similar roles.Strong SystemVerilog and UVM expertise.Familiarity with Linux and standard EDA tools.Thorough understanding of the pre-silicon design and verification flow.Excellent communication, documentation, and teamwork skills.Preferred / PlusProven experience with coverage closure.Background in debugging complex designs.Strong analytical and problem-solving mindset.Originally posted on Himalayas
Full Description
We’re looking for a Senior Verification Engineer to play a key role in verifying complex SoC and subsystem designs. You’ll work hands-on with design and architecture teams to ensure functionality, quality, and coverage goals are met across multiple projects.ResponsibilitiesAnalyze architectural specifications and define verification requirements.Develop and maintain UVM-based verification environments.Create detailed test plans and develop corresponding test cases.Debug functional issues and contribute to root-cause analysis.Collaborate closely with design and architecture teams to align milestones and quality metrics.QualificationsBachelor’s or Master’s degree in EE, CS, or a related field.7–10+ years of experience in verification or similar roles.Strong SystemVerilog and UVM expertise.Familiarity with Linux and standard EDA tools.Thorough understanding of the pre-silicon design and verification flow.Excellent communication, documentation, and teamwork skills.Preferred / PlusProven experience with coverage closure.Background in debugging complex designs.Strong analytical and problem-solving mindset.Originally posted on Himalayas